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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ADP3402 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2000 features handles all gsm baseband power management functions four ldos optimized for speci?c gsm subsystems charges back-up capacitor for real-time clock charge pump and logic level translators for 3 v and 5 v gsm sim modules thermally enhanced 6.1 mm 28-lead tssop package applications gsm/dcs/pcs handsets telematic systems ico/iridium terminals gsm power management system functional block diagram digital ldo vcc vrtc vtcxo pwronkey rowx pwronin reset analogon power-up sequencing and protection logic ADP3402 vbat refout agnd vcca rescap chron simbat cap+ cap 2 simprog simon simgnd resetin clkin dataio charge pump logic level translation buffer ref + i/o rst clk vsim rtc ldo xtal osc ldo analog ldo dgnd general description the ADP3402 is a multifunction power management system ic optimized for gsm cell phones. the wide input voltage range of 3.0 v to 7.0 v makes the ADP3402 ideal for both single cell li-ion and three cell nimh designs. the current consumption of the ADP3402 has been optimized for maximum battery life, featuring a ground current of only 230 m a when the phone is in standby (digital ldo, analog ldo, and sim card supply active). an undervoltage lockout (uvlo) prevents the startup when there is not enough energy in the battery. all four integrated ldos are optimized to power one of the critical sub-blocks of the phone. their novel anycap? architecture requires only very small output capacitors for stability, and the ldos are insensitive to the capacitors equivalent series resistance (esr). this makes them stable with any capacitor, including ceramic (mlcc) types for space-restricted applications. a step-up converter is implemented to supply both the sim module and the level translation circuitry to adapt logic signals for 3 v and 5 v sim modules. sophisticated controls are avail- able for power-up during battery charging, keypad interface and charging of an auxiliary back-up capacitor for the real-time clock. these allow an easy interface between ADP3402, gsm proces- sor, charger, and keypad. the 28-lead tssop package has been thermally enhanced to maximize power dissipation capability. furthermore, a reset circuit and a thermal shutdown function have been implemented to support reliable system design. anycap is a trademark of analog devices, inc.
C2C rev. 0 ADP3402Cspecifications electrical characteristics 1 parameter symbol conditions min typ max unit shutdown supply current i bat vbat = low (uvlo low) vbat = 2.7 v 3 20 m a vbat = high (uvlo high) vbat = 3.6 v, vrtc on 12 30 m a operating ground current i gnd vcc, vrtc, vcca, refout on minimum loads, vbat = 3.6 v 175 240 m a vcc, vrtc, vcca, refout and vsim on minimum loads, vbat = 3.6 v 230 340 m a all ldos and vsim on minimum loads, vbat = 3.6 v 260 400 m a all ldos and vsim on maximum loads, vbat = 3.6 v 15 ma uvlo characteristics uvlo on threshold vbat uvlo 3.2 3.3 v uvlo hysteresis 200 mv input characteristics input high voltage v ih pwronin and analogon 2 v pwronkey 0.7 3 vbat v input low voltage v il pwronin and analogon 0.4 v pwronkey 0.3 3 vbat v pwronkey input pullup resistance to vbat 15 20 25 k w chron characteristics chron threshold v t 2.38 2.48 2.58 v chron hysteresis resistance r in 2.38 < chron < v t 108 125 138 k w chron input bias current i b chron > v t 0.5 m a rowx characteristics rowx output low voltage v ol pwronkey = low 0.4 v i ol = 200 m a rowx output high leakage i ih pwronkey = high 1 m a current v(rowx) = 5 v shutdown thermal shutdown threshold 2 junction temperature 160 oc thermal shutdown hysteresis junction temperature 35 oc digital ldo (vcc) output voltage vcc line, load, temp 2.400 2.450 2.500 v line regulation d vcc 3 v < vbat < 7 v, min load 2 mv load regulation d vcc 50 m a < i load < 100 ma, 15 mv vbat = 3.6 v output capacitor 3 c o 2.2 m f analog ldo (vcca) output voltage vcca line, load, temp 2.710 2.765 2.820 v line regulation d vcca 3 v < vbat < 7 v, min load 2 mv load regulation d vcca 200 m a < i load < 130 ma, 15 mv vbat = 3.6 v output capacitor 3 c o 2.2 m f dropout voltage v do v o = v initial C 100 mv 215 mv i load = 130 ma ripple rejection d vbat/ f = 217 hz (t = 4.6 ms) 65 70 db d vcca vbat = 3.6 v output noise voltage v noise f = 10 hz to 100 khz 75 m v rms i load = 130 ma, vbat = 3.6 v (C20 c t a +85 c, vbat = 3 v to 7 v, c vbat = c simbat = c vsim = 10 m f, c vcc = c vcca = 2.2 m f, c vrtc = 0.1 m f, c vtcxo = 0.22 m f, c vcap = 0.1 m f, minimum loads applied on all outputs, unless otherwise noted)
C3C rev. 0 ADP3402 parameter symbol conditions min typ max unit crystal oscillator ldo (vtcxo) output voltage vtcxo line, load, temp 2.710 2.765 2.820 v line regulation d vtcxo 3 v < vbat < 7 v, min load 2 mv load regulation d vtcxo 100 m a < i load < 5 ma, 1 mv vbat = 3.6 v output capacitor 3 c o 0.22 m f dropout voltage v do v o = v initial C 100 mv 150 mv i load = 5 ma ripple rejection d vbat/ f = 217 hz (t = 4.6 ms) 65 72 db d vtcxo vbat = 3.6 v output noise voltage v noise f = 10 hz to 100 khz 80 m v rms i load = 5 ma, vbat = 3.6 v voltage reference (refout) output voltage v refout line, load, temp 1.192 1.210 1.228 v line regulation d v refout 3 v < vbat < 7 v, min load 2 mv load regulation d v refout 0 m a < i load < 50 m a, 0.5 mv vbat = 3.6 v ripple rejection d vbat/ f = 217 hz (t = 4.6 ms), 65 75 db d v refout vbat = 3.6 v maximum capacitive load c o 100 pf output noise voltage v noise f = 10 hz to 100 khz 40 m v rms vbat = 3.6 v real-time clock ldo/battery charger (vrtc) maximum output voltage vrtc i load 10 m a 2.400 2.450 2.500 v current limit i max 175 m a off reverse leakage current i l 2.0 v < vbat < uvlo 1 m a sim charge pump (vsim) output voltage for 5 v sim modules vsim 0 ma i load 10 ma 4.70 5.00 5.30 v simprog = high output voltage for 3 v sim modules vsim 0 ma i load 6 ma 2.82 3.00 3.18 v simprog = low gsm/sim logic translation (gsm interface) input high voltage (simprog, simon, v ih vcc C 0.6 v resetin, clkin) input low voltage (simprog, simon, v il 0.6 v resetin, clkin) dataio v il v ol (i/o) = 0.4 v, 0.230 v i ol (i/o) = 1 ma v ol (i/o) = 0.4 v, 0.335 v i ol (i/o ) = 0 ma v ih , v oh i ih , i oh = 10 m a vcc C 0.4 v i il v il = 0 v C0.9 ma v ol v il (i/o) = 0.4 v 0.420 v dataio pull-up resistance to vcc r in 16 20 24 k w
C4C rev. 0 ADP3402Cspecifications parameter symbol conditions min typ max unit sim interface vsim = 5 v rst v ol i = +200 m a 0.6 v rst v oh i = C20 m a vsim C 0.7 v clk v ol i = +200 m a 0.5 v clk v oh i = C20 m a 0.7 3 vsim v i/o v il 0.4 v i/o v ih , v oh i ih , i oh = 20 m a vsim C 0.4 v i/o i il v il = 0 v C0.9 ma i/o v ol i ol = 1 ma 0.4 v dataio 0.23 v vsim = 3 v rst v ol i = +200 m a 0.2 3 vsim v rst v oh i = C20 m a 0.8 3 vsim v clk v ol i = +20 m a 0.2 3 vsim v clk v oh i = C20 m a 0.7 3 vsim v i/o v il 0.4 v i/o v ih , v oh i ih , i oh = 20 m a vsim C 0.4 v i/o i il v il = 0 v C0.9 ma i/o v ol i ol = 1 ma 0.4 v dataio 0.23 v i/o pull-up resistance to vsim r in 81012k w max frequency (clk) f max c l = 30 pf 5 mhz prop delay (clk) t d 30 50 ns output rise/fall times (clk) t r , t f c l = 30 pf 9 18 ns output rise/fall times (i/o, rst) t r , t f c l = 30 pf 1 m s duty cycle (clk) d d clkin = 50% 47 53 % f = 5 mhz reset generator (reset) output high voltage v oh i oh = C15 m a vcc C 0.3 v output low voltage v ol i ol = C15 m a 0.3 v delay time per unit capacitance t d 1.0 ms/nf applied to rescap pin notes 1 all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc) methods . 2 this feature is intended to protect against catastrophic failure of the device. maximum allowed operating junction temperature is 125oc. operation beyond 125oc could cause permanent damage to the device. 3 required for stability. speci?cations subject to change without notice.
ADP3402 C5C rev. 0 absolute maximum ratings * voltage on any pin with respect to any gnd pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v, +10 v voltage on any pin may not exceed vbat, with the following exceptions: vrtc, vsim, cap+, pwronin, i/o, clk, rst storage temperature range . . . . . . . . . . . . C65 c to +150 c operating temperature range . . . . . . . . . . . C20 c to +85 c maximum junction temperature . . . . . . . . . . . . . . . . . 125 c q ja , thermal impedance (tssop-28) . . 2-layer board 90 c/w q ja , thermal impedance (tssop-28) . . 4-layer board 60 c/w lead temperature range (soldering, 60 sec) . . . . . . . . 300 c * this is a stress rating only, operation beyond these limits can cause the device to be permanently damaged. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ADP3402 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device pin configuration 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ADP3402 simgnd clkin resetin dataio simbat cap 2 vrtc vbat vcc pwronkey analogon chron rowx pwronin i/o rst simprog simon clk vsim cap+ agnd vcca refout reset rescap dgnd vtcxo pin function descriptions pin mnemonic function 1 vbat battery input voltage 2 vcc digital low dropout regulator 3 pwronkey power on/off key 4 analogon vtcxo enable 5 pwronin power on/off signal from microprocessor 6 rowx microprocessor keyboard output 7 chron charger on/off input 8 vrtc real-time clock supply/coin cell battery charger 9 capC negative side of boost capacitor 10 simbat battery input for the sim charge pump 11 dataio non-level-shifted bidirectional data i/o 12 resetin non-level-shifted sim reset 13 clkin non-level-shifted clock 14 simgnd charge pump ground 15 i/o level-shifted bidirectional sim data input/output 16 rst level-shifted sim reset 17 simprog vsim programming: low = 3 v, high = 5 v 18 simon vsim enable 19 clk level-shifted sim clock 20 vsim sim supply 21 cap+ positive side of boost capacitor 22 rescap reset delay timing cap 23 dgnd digital ground 24 vtcxo crystal oscillator low dropout regulator 25 reset main reset 26 refout reference output 27 vcca analog low dropout regulator 28 agnd analog ground ordering guide temperature package package model range description option ADP3402aru C20 c to +85 c 28-lead tssop ru-28a
ADP3402 C6C rev. 0 table i. ldo control logic inputs outputs uvlo chron pwronkey pwronin analogon vrtc vcc vcca refout vtcxo l x x x x off off off off off h h xxx ononononon hx l x x on on on on on h l h l x on off off off off hl h h lononononoff hl h h h on on on on on x = don't care bold denotes the active control signal. charger on threshold over temp en ref buffer vbat vref en gnd pg out digital ldo vcc 2.45v dgnd vrtc 2.45v vbat en gnd out vbat vref en gnd out power good rtc ldo xtal osc ldo analog ldo vbat vref en gnd out refout agnd vcca 2.765v vtcxo 2.765v + 1.210v uvlo adj uvlo vbat pwronkey rowx pwronin rescap reset chron analogon simbat cap+ cap 2 simprog simon simgnd resetin clkin dataio charge pump logic level translation vsim rst clk i/o en 3v/5v 20k v en ADP3402 reset generator figure 1. functional block diagram table ii. vsim control logic inputs outputs vcc reset simon simprog vsim off l x x off on l x x off on h l x off on h h l 3 v on h h h 5 v x = don't care
ADP3402 C7C rev. 0 vbat C v 350 300 100 37 4 i gnd C m a 56 250 200 150 pwronin, simon, and analogon pwronin and simon pwronin figure 2. ground current vs. battery voltage load current C ma 0 140 20 40 60 80 100 120 160 0 dropout voltage C mv 140 80 60 40 20 120 100 figure 3. vcca dropout voltage vs. load current load current C ma 80 0 dropout voltage C mv 70 40 30 20 10 60 50 0 12345 figure 4. vtcxo dropout voltage vs. load current vrtc C v 200 0 0 2.7 0.3 i rtc C m a 0.6 0.9 1.2 1.5 1.8 2.1 2.4 180 100 60 40 20 160 140 80 120 +85 8 c +25 8 c 2 20 8 c figure 5. rtc i/v characteristic voltage time C 100 m s/div vbat 100 mv/div 3.2 3.0 mlcc caps vcc 10 mv/div vcca 10 mv/div vtcxo 10 mv/div figure 6. line transient response, maximum loads voltage time C 100 m s/div 3.2 3.0 mlcc caps vbat (100 mv/div) vcc (10 mv/div) vcca (10 mv/div) vtcxo (10 mv/div) figure 7. line transient response, minimum loads
ADP3402 C8C rev. 0 voltage C 20mv/div time C 200 m s/div i load i = 100ma mlcc caps vcc i = 200 m a figure 8. vcc load step voltage C 20mv/div time C 100 m s/div i = 50 m a i load i = 130ma mlcc caps vcca figure 9. vcca load step voltage time C 50 m s/div pwronin and analogon (2v/div) vcca (100mv/div) vtcxo (100mv/div) vcc (100mv/div) figure 10. turn-on transients, minimum loads voltage time C 50 m s/div pwronin and analogon (2v/div) vcca (100mv/div) refout (100mv/div) vcc (100mv/div) vtcxo (100mv/div) figure 11. turn-on transients, maximum loads fre q uency C hz 80 70 0 4 100k 10 ripple rejection C db 100 1k 10k 60 50 10 40 30 20 vtcxo vcca vcc refout mlcc output caps vbat = 3.2v, full loads figure 12. ripple rejection vs. frequency vbat C v 80 0 2.5 3.3 2.6 ripple rejection C db 2.7 2.8 2.9 3.0 3.1 3.2 70 40 30 20 10 60 50 frequency = 217hz max loads vtcxo vcca refout vcc figure 13. ripple rejection vs. battery voltage
ADP3402 C9C rev. 0 analog gnd digital and sim gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 2.2 m f 100nf 28 27 26 25 23 22 21 20 19 18 17 16 15 ADP3402 100 v 10 m f r1 charger input r2 capacitor-type backup coin cell 10 m f sim pin of gsm processor 2.2 m f 10 m f 24 0.22 m f 100nf 10 m f clk to simcard rst to simcard i/o to sim card 100nf 1 li-ion or 3 nimh cells gsm processor gsm processor vbat vcc pwronkey analogon pwronin rowx chron vrtc capC simbat dataio resetin clkin simgnd agnd vcca refout vtcxo dgnd rescap cap+ vsim clk simon simprog rst i/o reset figure 15. typical application circuit frequency C hz 600 500 0 10 100k 100 voltage spectral noise density C nv/ hz 1k 10k 400 300 200 100 full load mlcc caps vcca tcxo ref figure 14. output noise density theory of operation the ADP3402 is a power management chip optimized for use with gsm baseband chipsets in handset applications. figure 1 shows a block diagram of the ADP3402. the ADP3402 contains several blocks: ? four low dropout regulators (digital, analog, crystal oscillator, real-time clock) ? reset generator ? buffered precision reference ? sim interface logic level translation (3 v/5 v) ? sim voltage supply ? power on/off logic ? undervoltage lockout these functions have traditionally been done either as a discrete implementation or as a custom asic design. ADP3402 combines the bene?ts of both worlds by providing an integrated standard product solution where every block is optimized to operate in a gsm environment while maintaining a cost competitive solution. figure 15 shows the external circuitry associated with the ADP3402. only a few support components, mainly decoupling capacitors, are required. input voltage the input voltage range for ADP3402 is 3 v to 7 v and optimized for a single li-ion cell or three nimh/nicd cells. the ADP3402 uses analog devices patented package thermal enhancement tech- nology, which allows 15% improvement in power handling capabil- ity over standard plastic packages. the thermal impedance ( q ja ) of the ADP3402 is 60 c/w. the charging voltage for a high capacity nimh cell can be as high as 5.5 v. power dissipation should be calculated at maximum ambient temperatures and battery voltage in order not to exceed the 125 c maximum allowable junction tem- perature. figure 16 shows the maximum total ldo output current as a function of ambient temperature and battery voltage. however, high battery voltages normally occur only when the battery is being charged and the handset is not in conversation mode. in this mode there is a relatively light load on the ldos. a fully charged li-ion battery is 4.25 v, where the ldos deliver the maximum 240 ma up to the max 85 c ambient temperature.
ADP3402 C10C rev. 0 ambient temperature C 8 c 300 0 2 20 0 total ldo current C ma 20 40 60 80 250 200 150 100 50 85 vbat = 5.5v vbat = 7v vbat = 6v vbat = 5v 4-layer board u ja = 60 8 c/w figure 16. total ldo load current vs. temperature and vbat low dropout regulators (ldos) the ADP3402 high-performance ldos are optimized for their given functions by balancing quiescent current, dropout voltage, line/load regulation, ripple rejection, and output noise. 2.2 m f tantalum or mlcc ceramic capacitors are recommended for use with the digital and analog ldos, and 0.22 m f for the tcxo ldo. digital ldo (vcc) the digital ldo (vcc) supplies all the digital circuitry in the handset (baseband processor, baseband converter, external memory, display, etc). the ldo has been optimized for very low quiescent current (30 m a maximum) at light loads as this ldo is on at all times. analog ldo (vcca) this ldo has the same features as the digital ldo. it has further- more been optimized for good low frequency ripple rejection for use with analog sections in order to reject the ripple coming from the rf power ampli?er. vcca is rated to 130 ma load which is suf?cient to supply the complete analog section of a baseband converter such as the ad6421/ad6425, including a 32 w earpiece. tcxo ldo (vtcxo) the tcxo ldo is intended as a supply for temperature com- pensated crystal oscillator, which needs its own ultralow noise supply. the output current is rated to 5 ma for the tcxo ldo. rtc ldo (vrtc) the rtc ldo charges a capacitor-type backup coin cell to run the real-time clock module. it has been targeted to charge elec- tric double layer capacitors such as the pas621 from kanebo. the pas621 has a small physical size (6.8 mm diameter) and a nominal capacity of 0.3 f, giving many hours of backup time. ADP3402 gsm processor vrtc pwron pwronin coin cell vrtc rtc module figure 17. connecting vrtc and poweronin to the chipset the ADP3402 supplies current both for charging the coin cell and for the rtc module when the digital supply is off. the nominal charging voltage is 2.45 v, which ensures long cell life while obtain- ing in excess of 90% of the nominal capacity. in addition, it features a very low quiescent current (10 m a) since this ldo is running all the time, even when the handset is switched off. it also has reverse current protection with low leakage which is needed when the main battery is removed and the coin cell supplies the rtc module. reference output (refout) the reference output is a low noise, high precision reference with a guaranteed accuracy of 1.5% over temperature. the reference can be fed to the baseband converter, such as the ad6425, improving the absolute accuracy of the converters from 5% to 1.5%. this signi?cantly reduces calibration time needed for the baseband converter during production. sim interface the sim interface generates the needed sim voltageeither 3 v or 5 v, dependent on sim type, and also performs the needed logic level translation. quiescent current is low, as the sim card will be powered all the time. note that dataio and i/o have integrated pull-up resistors as shown in figure 18. see table ii for the control logic of the charge pump output, vsim. resetin clkin dataio rst clk i/o level shift vcc vsim ADP3402 level shift vcc vcc vsim vsim figure 18. schematic for level translators power-on/-off ADP3402 handles all issues regarding power-on/-off of the hand- set. it is possible to turn on the ADP3402 in three different ways: ? pulling pwronkey low ? pulling pwronin high ? chron exceeds threshold pulling pwronkey key low is the normal way of turning on the handset. this will turn on all the ldos as long as pwronkey is held low. the microprocessor then starts and pulls pwronin high after which pwronkey can be released. pwronin going high will also turn on the handset. this is the case when the alarm in the rtc module expires. an external charger can also turn on the phone. the turn-on threshold and hysteresis can be programmed via external resistors to allow full ?exibility with any external charger and battery chem- istry. these resistors are referred to as r1 and r2 in figure 15. undervoltage lockout (ulvo) the uvlo function in the ADP3402 prevents startup when the initial voltage of the main battery is below the 3.2 v threshold. if the battery is this low with no load, there will be little or no capacity left. when the battery is greater than 3.2 v, as with the insertion of a fresh battery, the uvlo comparator trips, the
ADP3402 C11C rev. 0 rtc ldo is enabled, and the threshold is reduced to 3.0 v. this allows the handset to start normally until the battery volt- age decays to 3.0 v open circuit. once the 3.2 v threshold is exceeded, the rtc ldo is enabled. if, however, if the backup coin cell is not connected, or is damaged or discharged below 1.5 v, the rtc ldo will not start on its own. in this situation, the rtc ldo will be started by enabling the vcc ldo. once the system is started, i.e., the phone is turned on and the vcc ldo is up and running, the uvlo function is entirely disabled. the ADP3402 is then allowed to run down to very low battery voltages, typically around 2 v. the battery voltage is normally monitored by the microprocessor and usually shuts the phone off at around 3.0 v. if the phone is off, i.e., the vcc ldo is off, and the battery voltage drops below 3.0 v, the uvlo circuit disables startup and the rtc ldo. this is implemented with very low quies- cent current, typically 3 m a, to protect the main battery against any damage. nimh batteries can reverse polarity if the 3-cell battery voltage drops below 3.0 v and a current of more than about 40 m a continues to ?ow. lithium ion batteries will lose their capacity, although the built-in safety circuits normally present in these cells will most likely prevent any damage. reset ADP3402 contains reset circuitry that is active both at power-up and at power-down. reset is held low at power-up. an inter- nal power-good signal starts the reset delay. the delay is set by an external capacitor on rescap: tc reset rescap = 10 . ms/nf a 100 nf capacitor will produce a 100 ms reset time. at power- off, reset will be kept low to prevent any spurious microproces- sor starts. the current capability of reset is low (a few hundred na) when vcc is off, to minimize power consumption. there- fore, reset should only be used to drive a single cmos input. when vcc is on, reset will drive about 15 m a. overtemperature protection the maximum die temperature for ADP3402 is 125 c. if the die temperature exceeds 160 c, the ADP3402 will disable all the ldos except the rtc ldo, which has very limited current capabilities. the ldos will not be re-enabled before the die temperature is below 125 c, regardless of the state of pwronkey, pwronin, and chron. this ensures that the handset will always power-off before the ADP3402 exceeds its absolute maximum thermal ratings. applications information input capacitor selection for the input voltage, vbat, of the ADP3402, a local bypass capacitor is recommended. use a 5 m f to 10 m f, low esr capaci- tor. multilayer ceramic chip capacitors provide the best combina- tion of low esr and small size, but may not be cost effective. a lower cost alternative may be to use a 5 m f to 10 m f tantalum capacitor with a small (1 m f to 2 m f) ceramic in parallel. ldo capacitor selection the performance of any ldo is a function of the output capaci- tor. the digital and analog ldos require a 2.2 m f capacitor and the tcxo ldo requires a 0.22 m f capacitor. larger values may be used, but the overshoot at startup will increase slightly. if a larger output capacitor is desired, be sure to check that the overshoot and settling time are acceptable for the application. all the ldos are stable with a wide range of capacitor types and esr due to analog devices anycap technology. the ADP3402 is stable with extremely low esr capacitors (esr ~ 0), such as multilayer ceramic capacitors, but care should be taken in their selection. note that the capacitance of some capacitor types show wide variations over temperature or with dc voltage. a good quality dielectric, x7r or better, is recommended. the rtc ldo has a rechargeable coin cell or an electric double- layer capacitor as a load, but a 0.1 m f ceramic capacitor is recom- mended for stability and best performance. charge pump capacitor selection for the input (simbat) and output (vsim) of the sim charge pump, use 10 m f low esr capacitors. the use of low esr capaci- tors improves the noise and ef?ciency of the sim charge pump. multilayer ceramic chip capacitors provide the best combination of low esr and small size but may not be cost effective. a lower cost alternative may be to use a 10 m f tantalum capacitor with a small (1 m f to 2 m f) ceramic capacitor in parallel. for the lowest ripple and best ef?ciency, use a 0.1 m f, ceramic capacitor for the charge pump ?ying capacitor (cap+ and capC). a good quality dielectric, such as x7r is recommended. setting the charger turn-on threshold the ADP3402 can be turned on when the charger input exceeds a programmable threshold voltage. the chargers threshold and hysteresis are set by selecting the values for r1 and r2 shown in figure 15. the turn-on threshold for the charger is calculated using: v rr rr rv chr hys hys t = + ? ? ? ? + ? ? 2 2 11 where v t is the chron threshold voltage and r hys is the chron hysteresis resistance. the hysteresis is determined using: v v r r hys t hys = 1 combining the above equations and solving for r 1 and r 2 gives the following formulas: r r v v hys t hys 1 = r rr v v rr hys chr t hys 2 1 11 = - ? ? ? ? - example: r 1 = 10 k w and r 2 = 30.2 k w gives a charger thresh- old (not counting the drop in the power schottky diode) of 3.5 v 160 mv with a 200 mv 30 mv hysteresis. charger diode selection the diode shown in figure 15 is used to prevent the battery from discharging into the charger turn-on setting resistors, r1 and r2. a schottky diode is recommended to minimize the voltage difference from the charger to the battery and the power dissipation. choose a diode with a current rating high enough to handle both the bat- tery charging current and the current the ADP3402 will draw if powered up during charging. the battery charging current is de- pendent on the battery chemistry, and the charger circuit. the ADP3402 current will be dependent on the loading.
C12C rev. 0 c3762C8C1/00 (rev. 0) printed in u.s.a. ADP3402 printed circuit board layout considerations use the following general guidelines when designing printed circuit boards: 1. split the battery connection to the vbat and simbat pins of the ADP3402. use separate traces for each connection and locate the input capacitors as close to the pins as possible. 2. sim input and output capacitors should be returned to the simgnd and kept as close as possible to the ADP3402 to minimize noise. traces to the sim charge pump capacitor should be kept as short as possible to minimize noise. 3. vcca and vtcxo capacitors should be returned to agnd. 4. vcc and vrtc capacitors should be returned to dgnd. 5. split the ground connections. use separate traces or planes for the analog, digital, and power grounds, and tie them together at a single point, preferably close to the battery return. outline dimensions dimensions shown in inches and (mm). 28-lead thin shrink small outline (tssop) (ru-28a) 0.244 (6.20) 0.236 (6.00) 28 15 14 1 0.386 (9.80) 0.378 (9.60) 0.325 (8.25) 0.313 (7.95) pin 1 seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0374 (0.95) 0.0335 (0.85) 0.0078 (0.200) 0.0035 (0.090) 0.030 (0.75) 0.020 (0.50) 8 8 0 8

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